What is Hardware Architecture AN-RAX?
The integrated circuits used in the C-DOT 256P AN-RAX hardware have low power dissipation and high operational reliability. The components used are based on Metal-Oxide-Semiconductor (MOS), Complementary MOS (CMOS), Low-Power Schottky Transistor-Transistor Logic (LSTTL), and bipolar technologies. All the system circuitry has been packaged into seven card types. On the broad level, these could be divided into the following categories:
- Terminal Interfaces
Subscriber Line Card (LCC/CCM)
- Controller Cards
AN-RAX Controller Card (ARC)
AN-RAX Interface Card (ARI)
Signalling Processor Card (SPC) or Integrated Signalling Processor Card(ISP)
- Service Cards
RAX Terminal Tester Card (RTC)
- Power Supply Unit (PSU-I)
C-DOT 256P AN-RAX uses Subscriber Line Card (LCC/CCM) to provide Analog Terminal Interface. Each terminal interface card caters to 8 terminations. Four cards make a Terminal Group (TG) which is associated with PCM 32 channel link towards the ARC card. Signaling information is multiplexed and placed on 4 wire ABCD signaling bus toward SPC/ISP card. Subscriber Line Card (LCC/CCM) (Ref. Fig. 4.1)
Line Circuit Card (LCC) is used to interface ordinary subscriber lines. Fig. 4.1 gives the detailed block diagram of this card.
The Line Circuit Card performs a set of functions collectively termed as BORSCHT, signifying:
B – Battery Feed
O – Overvoltage Protection
R – Ringing
S – Supervision
C – Coding
H – Hybrid Conversion
T – Testing
- Battery Feed
A -48V_+ 4V battery with the current limiting facility is provided on each line for signaling purposes and for energizing the microphone.
- Overvoltage Protection
A hybrid transformer and surge arresters across Tip and Ring provide protection against overvoltages.
Ringing is extended to subscribers under the control of Signalling Processor (SPC/ISP card), through the contacts of an energized relay. The Ring is tripped when the off-hook condition is detected.
On/Off-hook detection and dialing make/break are encoded and passed on to SPC/ISP card as the scan information from the subscriber lines.
Coding refers to the encoding of analog voice to digital form (8 bit, A-law PCM) through a coder/decoder (codec). Codec outputs of 32 codecs of each Terminal Group are time-division multiplexed to form a PCM 32 channel at 2.048 Mbps.
- Hybrid Conversion
2-wire to 4-wire conversion is done before coding for full-duplex (voice) operation.
Metallic access is provided on subscriber lines for routine tests. (Tests Access Relays)
- Coin Collection Box (CCB) interface card is an ordinary LCC card with an additional reversal relay per subscriber to extend reversal on called party answer. This card is basically used to cater to special requirements of PCOs and PABXs. However, this card can also be used as a line circuit card (LCC).
Coin Collection Box with Metering (CCM) card is also the same as LCC/CCB card except that it has got extra hardware to generate and feed 16 kHz pulses towards subscriber premise. This card is basically used to interface STD PCOs or special subscribers having home metering requirements. However, in CCM card out of eight ports only last two i.e., Port no. 7 and 8 are equipped with a 16 kHz pulse generator. Therefore, only two subscribers per CCM card may have this provision. Rest of the ports are used for ordinary subscribers or coin collection box type. This card as a whole can be used as LCC.
The ARC card functions as the main controller of the AN-RAX. It performs the time switching of voice/data slots between line cards. Towards the line cards, it gives the card selected, subscriber select, clock, and sync signals. It has an interface towards the SPC/ISP card for providing a signaling interface to the line cards. It has an interface towards the ARI (AN-RAX Interface) card used in the slave frame to support voice and signaling interface for the line cards in the slave frame. The card exists in copy duplication and occupies slots 12 and 15 of the master frame in 256P AN-RAX. It interfaces with RTC (RAX Terminal Tester) card for supporting terminal testing in AN-RAX.
The Functional Blocks of ARC are :
Processor and memory block
Time switch and service circuits block
SPC/ISP interface block
The digital trunk interface block
DT clock extraction and generation block
ARI interface block
PSU interface block
- Processor and Memory Block
This card is designed using Morotola’s 68392 processor in MASTER-SLAVE configuration as shown in Fig. 4.3. The processor is clocked at 16.384 MHz. The processor clock is generated using a crystal oscillator. The reset circuitry uses a micro monitor chip, which asserts reset when VCC is out of range or when manual reset switch is activated or when the strobe is missing. The 16.38 MHz processor input clock is divided by two and given as strobe to the micro monitor chip.
The master IMP’s SCC1 is used as an HDLC link towards RTC card or ETT card. SCC will operate in NMSI mode at 64 Kbps for RTC card and in PCM mode at 2 Mbps for ETT card.
Master IMP’s SCC2 is used as an HDLC link towards duplicate ARC card. The speed of this link is 64Kbps.
Master IMP’s SCC3 is used as a debugging ACIA link. The speed of this link is software programmable and normally is 9600 baud.
SCP of Master IMP is used to communicate with tester card in ARC card tester. Slave IMP’s SCC1 & SCC2 are used in PCM mode.
SCC1 is used to handle HDLC messages (V5.2) on DT0 link. SCC2 is used to handle HDLC messages (V5.2) on the DT1 link.
Slave IMP’s SCC3 is used as an ACIA link for providing MMI through a dumb terminal. The speed of this link is S/W programmable and normally is 9600 baud.
Slave IMP’s SCP is used to access DT ASIC (CPRAC) registers in order to control and monitor the DT links. In this communication, the processor is always the master.
Master IMP’s Watchdog timer is used as a software watchdog. The timer reference register is initialized with the time-out value. The software periodically resets the counter so that the timer count register never reaches the time-out count. If the software fails to reset the timer count register within the stipulated time, timer count reaches the reference count and a level 7 interrupt is raised to IMP and also to mate ARC card.
Timer 1 of master IMP is used as RTC (Real Time Clock). This timer can be programmed to periodically interrupt the processor at regular intervals.
Timer 2 of master IMP is used as a counter or timer in ARC card tester.
Timer 1 of the slave IMP is used as a DT0 slip detector/counter. The counter can be programmed to count the number of slip’s occurring in DT link for statistical health monitoring of the DT link
Timer 2 of the slave IMP is used as a DT1 slip detector/counter.
Real Time Calendar
The ARC card has been provided with one Real Time Clanedar chip, which can count the time, date, day of the week & Year. At present, this is not used.
Control and Status Registers Block
The Port A and Port B registers of master and slave processors are used as control and status registers. Some of the control and status registers are implemented externally using programmable devices. They are used to latch the status of all interrupts and to clear the latched status, program loop back bits and to latch ID bits from the back plane.
Interrupt Logic Block
This block receives all error interrupts and peripheral interrupts, prioritizes them and inputs to master IMP. Some interrupts are given directly to the Port B interrupt pins of master and slave at level 4. All the events are latched and the status is provided to the processor through status registers. The processor can clear the latched events by appropriately setting the corresponding bits in the control registers. Interrupt from SPC/ISP card master frame and slave frame are combined and presented at level 5. Error signals from Master and slave PSU cards are combined to generate a level 1 interrupt to the processor.
This card supports onboard memory of 1MB FLASH or 2MB EPROM, 1MB RAM and 64 KB/1MB NVRAM. Chip selects are generated using master and slave IMP’s chip select registers and glue logic. One jumper is provided to select either FLASH or EPROM and one more jumper is provided to select NVRAM capacity.
- Time Switch and Service Circuits Block This card have a 2K by 2K time switch, implemented in FPGA. The time switch is operated at 8MHz speed and is used in 16-bit processor mode. One input link is programmed as the conference link. Speed of the conference link is 8Mbps and it supports 32 Four party conferencing. 12 out of 16 possible I/O links are used as shown below.
The input links of the time switch are :
- One conference link (8Mbps) for 32 four party conferencing
- One 8Mbps link from Tone, Announcement, MF and DTMF generation circuit.
- Eight 2Mbps links (TG (0)_IN to TG (7)_IN) from TGs.
- One 2Mbps link for DT and ETT messages
- Two 2Mbps links from DTs
The output links of the time switch are :
- One link for conferencing (8Mbps)
- Eight 2 Mbps links (TG (0)_OUT to TG (7)_OUT) towards TGs.
- One 2 Mbps link for DT and ETT messages
- Two 2 Mbps links towards DTs.
Tone, Announcement, MF-DTMF Generation
The MF, DTMF, tone and announcement samples are stored in EPROMs. The EPROMs are addressed by free running counter chains, which are implemented in FPGAs. Bank control EPROMs are used to address different pages of the stored data. The parallel output of EPROMs is converted to serial link at 8 Mbps and connected to time switch as shown in Fig. 4.6.
- SPC/ISP Interface Block
This card interfaces with SPC/ISP card in the master frame to provide a signaling interface for the 128 ports. Chip select for the SPC/ISP card is given by the external logic implemented. 3 address bits, 8 data bits, and one read-write bit are provided for configuring the SPC/ISP registers. IM Clock signal is provided for SPC/ISP operations and processor synchronized clock signal is provided for memory operations.
This card also has an interface towards the SPC/ISP card in the slave frame. This interface is through the ARI (AN-RAX Interface) card present in the slave frame.
- Digital Trunk Interface Block
The card supports two E1 links in CCS mode. One CPRAC (C-DOT Primary Rate Access Controller) is used. The E1 links conform to G.703, G.704, F.706, and G.732 and are supported on 120Ohm symmetric twisted pair interface.
CPRAC has two sets of 16 registers to individually configure the two digital trunks. These registers are used to control and monitor the links.
The clock extracted from the digital trunk is multiplied (using PLL) to generate the 8MHz clock. Refer Fig. 4.8. The error status signals like receiver loss of sync (RLOS), receive remote alarm (RRA) are reported through interrupts. Loop back provision is given for both the DTs through relays, which can be used for diagnostics purposes by setting the loop back bits in the control and status registers. The relays are also used to ensure that only the active ARC card will drive the physical E1 links.
- DT Clock Extraction and Generation Block
The CPRAC gives out the extracted clock from both the digital trunks. One of these is selected and input to the PLL. Thus the on board VCXO clock is made to lock to the extracted clock. Refer Fig. 4.8.
Clock Selection Block
The following clock and sync selections are possible :
a) Network synchronized clock and sync from active ARC card
b) Network synchronized clock and sync from duplicate ARC card
c) No clock
The processor will select one out of these clocks depending on the mode of operation. Hardware error generation logic is implemented to generate the error for the absence of the clock or improper clock. Selecting the option `c’ can test this logic.
Refer PCM clock generation, selection, Detection & Distribution Block below:
ARI Interface Block
The voice and signaling interface for the line cards in the slave frame is achieved through this interface. The processor bus and the necessary control signals required for the SPC/ISP card in the slave frame are exchanged in the differential form to support the 128 ports in the slave frame. The status of the PSU cards in the slave frame is made available at the ARC card through this interface. The signals between ARC and the corresponding copy of ARI are exchanged through both backplane interface cable and front-end 60 pin FRC cable.
- PSU Interface Block
The card draws power from the backplane 5V supplied by the PSU cards. The PSUERR and BATTERY LOW signal from the copy 0 and copy 1 PSU cards interrupts the processor whenever PSU output voltage or the battery goes out of range.
- Testability and Faulty CoverageAll parts of the processor logic can be tested by checking access to the devices. The loopback feature is provided for all the PCM links. MF, DTMF generation logic can be tested by switching the tones to the PCM link.
DT logic can also be tested by pattern insertion/extraction from time switch and by enabling DT relay loopback. DT events such as RLOS and SLIP are given as interrupt to the processor so that the health status of the DTs can always be monitored.
The critical signals in the ARC card are given the fault coverage. The software sanity is monitored with the help of a watchdog timer. The presence and the tolerance of the 8 MHz clock are always monitored and indicated to the processor as the hardware Error. The bus error signal is generated when there is access to a non-existent memory location, write access to PROM and all the IMP access in which DTACK is not asserted by IMP within a programmed number of wait states from address strobe active.
All the PSU errors are given as interrupt to the processor so that alarms can be raised to indicate the PSU failure. The card presence of the ARI is also given as level 4 interrupt.
The Watchdog, Hardware error signal, Active to Passive transition and manual reset of the self copy is given as interrupt to mate card so that copy switchover can be achieved when one copy fails.
- AN-RAX Interface Card
ARI organization can be split into the following blocks
- LCC interface block
- SPC (Slave) – interface block
- PSU – interface block
- ARC interface block
- LCC Interface Block
This block provides an interface to the voice signals (PCM links), 2M PCM clock, terminal card select signals, terminals address signals, status signal (HE, A/P, WDOG), from ARC to ARI & vice versa. It receives a signal from ARC in a differential form and converts them into single-ended signals. Similarly, signals received from LCC cards in the slave frame are converted into differential form and then sent to ARC in the same plane of the master frame.
- SPC (Slave) – Interface Block
This block receives the differential bi-directional data bus from ARC and converts them into single-ended form and vice versa. Similarly, differential address and control signals received from ARC are converted into single-ended form. These signals are buffered and sent towards SPC in the same plane of the slave frame. The interrupt from SPC is buffered converted to differential signal, buffered and sent towards ARC in the same plane of the master frame.
- PSU-Interface Block
This block receives the power supply error signals from both PSUs in the slave frame. These signals are buffered and sent to ARC in the same plane of the master frame.
ARC Interface Block
The differential 16.384 MHz PCLK, differential chip select signal from ARC are converted into single-ended form and given to EPLD. The differential spare inputs from ARC are converted to single-ended form and given to EPLD. The spare outputs from EPLD are converted to differential form and given to ARC in the same plane of the master frame.
- LCC Interface Block
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