What is the Digital Switching System?
A Digital switching system, in general, is one in which signals are switched in digital form. These signals may represent speech or data. The digital signals of several speech samples are time-multiplexed on a common media before being switched through the system.
To connect any two subscribers, it is necessary to interconnect the time-slots of the two speech samples which may be on the same or different PCM highways. The digitalized speech samples are switched in two modes, viz., Time Switching and Space Switching. This Time Division Multiplex Digital Switching System is popularly known as Digital Switching System.
In this handout, general principles of time and space switching are discussed. A practical digital switch, comprising of both time and space stages, is also explained.
4.1 Time and Space Switching
Generally, a digital switching system several time division multiplexed (PCM) samples. These PCM samples are conveyed on PCM highways (the common path over which many channels can pass with separation achieved by time division.). The switching of calls in this environment requires placing digital samples from one time-slot of a PCM multiplex in the same or different time-slot of another PAM multiplex.
For example, PCM samples appearing in TS6 of I/C PCM HWY1 are transferred to TS18 of O/G PCM HWY2, via the digital switch, as shown in Fig1.
The interconnection of time-slots, i.e., switching of digital signals can be achieved using two different modes of operation. These modes are: –
- Space Switching
- Time switching
Usually, a combination of both modes is used.
In the space-switching mode, corresponding time-slots of I/C and O/G PCM highways are interconnected. A sample, in a given time-slot, TSi of an I/C HWY, says HWY1, is switched to the same time-slot, TSi of an O/G HWY, SAY HWY2. Obviously, there is no delay in switching off the sample from one highway to another highway since the sample transfer takes place in the same time-slot of the PCM frame.
Time Switching, on the other hand, involves the interconnection of different time-slots on the incoming and outgoing highways by re-assigning the channel sequence. For example, a time-slot TSX of an I/C Highway can be connected to a different time-slot., TSy, of the outgoing highway. In other words, a time switch is, basically, a time-slot changer.
The Digital Space Switch consists of several input highways, X1, X2,…Xn and several output highways, Y1, Y2,………….Ym, interconnected by a crosspoint matrix of n rows and m columns. The individual crosspoint consists of electronic AND gates. The operation of an appropriate crosspoint connects any channel, a, of I/C PCM highway to the same channel, a, of O/G PCM highway, during each appropriate time-slot which occurs once per frame as shown in Fig 2. During other time-slots, the same crosspoint may be used to connect other channels. This crosspoint matrix works as a normal space divided matrix with full availability between incoming and outgoing highways during each time-slot.
Each crosspoint column, associated with one O/G highway, is assigned a column of control memory. The control memory has as many words as there is time-slot per frame in the PCM signal. In practice, this number could range from 32 to 1024. Each crosspoint in the column is assigned a binary address so that only one crosspoint per column is closed during each time-slot. The binary addresses are stored in the control memory, in the order of time-slots. The word size of the control memory is x bits, so that 2x = n, where n is the number of cross points in each column.
A new word is read from the control memory during each time-slot, in a cyclic order. Each word is read during its corresponding time-slot, i.e., Word 0 (corresponding to TS0), followed by word 1 (corresponding to TS1) and so on. The word contents are contained in the vertical address lines for the duration of the time-slot. Thus, the cross point corresponding to the address is operated during a particular time-slot. This cross-point operates every time the particular time-slot appears at the inlet in successive frames. normally, a call may last for around a million frames.
As the next time-slot follows, the control memory is also advanced by one step, so that during each new time-slot new corresponding words are read from the various control memory columns. This results in the operation of a completely different set of cross points being activated in different columns. Depending upon the number of time-slots in one frame, this time-division action increases the utilization of cross point 32 to 1024 times compared with that of the conventional space-divided switch matrix.
Consider the transfer of a sample arriving in TS7 of I/C HWY X1 to O/G HWY Y3. Since this is a space switch, there will be no reordering of time i.e., the sample will be transferred without any time delay, via the appropriate cross point. In other words, the objective is to connect the TS7 of HWY X1 and TS7 of HWY Y3.
The central control (CC) selects the control memory column corresponding output highway Y3. In this column, the memory location corresponding to the TS7 is chosen. The address of the cross point is written in this location, i.e., 1, in binary, is written in location 7, as shown in fig 2.This cross point remains operated for the duration of the time-slot TS7, in each successive frame till the call lasts.
For the disconnection of call, the CC erases the contents of the control memory locations, corresponding to the concerned time-slots. The AND gates, therefore, are disabled and transfer of samples is halted.
Practical Space Switch
In a practical switch, the digital bits are transmitted in parallel rather than serially, through the switching matrix.
In a serial 32 time-slots PCM multiplex, 2048 Kb/s are carried on a single wire sequentially, i.e., all the bits of the various time-slots follow one another. This single wire stream of bits, when fed to Serial to Parallel Converter is converted into an 8-wire parallel output. For example, all 8 bits corresponding to TS3 serial input are available simultaneously on eight output wires (one bit on each output wire), during just one-bit period, as shown in fig.3. This parallel output on the eight wires is fed to the switching matrix. It can be seen that during one full time-slot period, only one bit is carried on each output line, whereas 8 bits are carried on the input line during this period. Therefore, bit rate on individual output wires is reduced to 1/8th of input bit rate=2048/8=256Kb/s
Due to the reduced bit rate in parallel mode, the cross point is required to be operated only for 1/8th of the time required for serial working. It can, thus, be shared by eight times more channels, i.e., 32 x 8 = 256 channels, in the same frame.
However, since the eight bits of one TS are carried on eight wires, each
cross point has eight switches to interconnect eight input wires to eight output wires. Each cross point (all the eight switches) will remain operated now for the duration of one bit only, i.e., only for 488 ns (1/8th of the TS period of 3.9 µs).
For example, to connect 40 PCM I/C highways, a matrix of 40x 40 = 1600
cross points each having a single switch is required in serial mode working. Whereas in parallel mode working, a matrix of (40/8 x 40/8) = 25 cross point is sufficient. As eight switches are required at each cross point 25 x 8 = 200 switches only are required. Thus, there is a reduction of the matrix by 1/8th in parallel mode working, hence a reduction in size and cost of the switching matrix.
4.3 Digital Time Switch
A Digital Time Switch consists of two memories, viz., a speech or buffer memory to store the samples till destination time-slots arrive, and control or connection or address memory to control the writing and reading of the samples in the buffer memory and directing them on to the appropriate time-slots.
Speech memory has as many storage locations as the number of time-slots in input PCM, e.g., 32 locations for 32 channel PCM system.
The writing/reading operations in the speech memory are controlled by the Control Memory. It has the same number of memory locations as for speech memory, i.e., 32 locations for 32 channel PCM system. Each location contains the address of one of the speech memory locations where the channel sample is either written or read during a time-slot. These addresses are written in the control memory of the CC of the exchange, depending upon the connection objective.
A Time-Slot Counter which usually is asynchronous binary counter is used to count the time-slots from 0 to 31, as they occur. At the end of each frame, It gets reset and the counting starts again. It is used to control the timing for writing/reading of the samples in the speech memory.
Consider the objective that TS4 of incoming PCM is to be connected to TS6 of outgoing PCM. In other words, the sample arriving in TS4 on the I/C PCM has to be delayed by 6 – 4 = 2 time-slots, till the destination time-slot, viz., TS6 appears in the O/G PCM. The required delay is given to the samples by storing it in the speech memory. The I/C PCM samples are written cyclically i.e. sequentially time-slot wise, in the speech memory locations. Thus, the sample in TS4 will be written in location 4, as shown in fig.4.
The reading of the sample is controlled by the Control Memory. The Control Memory location corresponding to output time-slot TS6 is 6. In this location, the CC writes the input time-slot number, viz.,4, in binary. These contents give the read address for the speech memory, i.e., it indicates the speech memory locations from which the sample is to be read out, during the reading cycle.
When the time-slot TS6 arrives, the control memory location 6 is read. Its content addresses location 4 of the speech memory in the read mode and the sample is read on to the O/G PCM.
In every frame, whenever time-slot 4 comes a new sample will be written in location 4. This will be read when TS6 occurs. This process is repeated until the call lasts.
For the disconnection of the call, the CC erases the contents of the control memory location to halt the further transfer of samples.
Time switch can operate in two modes, viz.,
- Output associated control
- Input associated control
4.3.1 Output associated control
In this mode of working, 2 samples of I/C PCM are written cyclically in the speech memory locations in the order of time-slots of I/C PCM, i.e., TS1 is written in location 1, TS2 is written in location 2, and so on, as discussed in the example of Sec.4.2.
The contents of speech memory are read on output PCM in the order specified by control memory. Each location of control memory is rigidly associated with the corresponding time-slot of the O/G PCM and contains the address of the TS of incoming PCM to be connected to. The control memory is always read cyclically, in synchronism with the occurrence of the time-slot. The entire process of writing and reading is repeated in every frame until the call is disconnected.
It may be noticed that the writing in the speech memory is sequential and independent of the control memory, while reading is controlled by the control memory, i.e., there is a sequential writing but controlled reading.
4.3.2 Input associated control
Here, the samples of I/C PCM are written in a controlled way, i.e., in the order specified by control memory, and read sequentially.
Each location of control memory is rigidly associated with the corresponding TS of I/C PCM and contains the address of TS of O/G PCM to be connected to.
The previous example with the same connection objective of connecting TS4 of I/C PCM to TS6 of O/G PCM may be considered for its restoration. Location 4 of the control memory is associated with incoming PCM TS4. Hence, it should contain the address of the location where the contents of TS4 of I/C PCM are to be written in speech memory. A CC writes the number of the destination TS, viz., 6 in this case, in location 4 of the control memory. The contents of TS4 are, therefore, written in the location of speech memory, as shown in fig5.
The contents of speech memory are read in the O/G PCM in a sequential way, i.e., location 1 is read during TS1, location 2 is read during TS2, and so on. In this case, the contents of location 6 will appear in the output PCM at TS6. Thus the input PCM TS4 is switched to output PCM TS6. In this switch, there is sequential reading but controlled writing.
4.4 Time Delay Switching
The writing and reading, of all time-slots in a frame, has to be completed within one frame time period (before the start of the next frame). A TS of incoming PCM may, therefore, get delayed by a time period ranging from 1 TS to 31 TS periods, before being transmitted on outgoing PCM. For example, consider a case when TS6 of incoming PCM is to be switched to TS5 in outgoing PCM. In this case, switching can be completed in two consecutive frames only, i.e., 121 microseconds for a 32 channel PCM system. However, this delay is imperceptable to human beings.
4.5 Non-Blocking feature of a Time Switch
In a Time Switch, there are as many memory locations in the control and speech memories as there are time-slots in the incoming and outgoing PCM highways, i.e., corresponding to each time-slot in incoming highway, there is a definite memory location available in the speech and control memories. Similarly, corresponding to each time-slot in the outgoing highway there is a definite memory location available in the control and speech memories. This way, corresponding to free incoming and outgoing time-slots, there is always a free path available to interconnect them. In other words, there is no blocking in a time switch.
4.6 Two Dimensional Switching
Though the electronic cross points are not so expensive, the cost of accessing and selecting them from external pins in a Space Switch becomes prohibitive as the switch size increases. Similarly, the memory location requirements rapidly go up as a Time Switch is expanded, making it uneconomical. Hence, it becomes necessary to employ a number of stages, using small switches as building blocks to build a large network. This would result in the necessity of changing both the time-slot and highway in such a network. Hence, the network, usually, employs both types of switches viz., space switch and time switch, and. therefore, is known as a two-dimensional network. These networks can have various combinations of the two types of switches and are denoted as TS, STS, TSST, etc.
Though to ensure full availability, it may be desirable to use only T stages. However, the networks having the architecture of TT, TTT, TTTT, etc., are uneconomical, considering the acceptability of tolerable limits of blocking, in a practical network. Similarly, a two-stage two-dimensional network, TS or ST, is basically suitable for very low capacity networks only. The most commonly used architecture has three stages, viz., STS or TST. However, in certain cases, their derivatives, viz., TSST, TSSST, etc., may also be used.
An STS network has relatively simpler control requirements and hence, is still being favored for low capacity networks, viz., PBX exchanges. As the blocking depends mainly on the outer stages, which are space stages, it becomes unsuitable for high capacity systems.
A TST network has lesser blocking constraints as the outer stages are timed stages that are essentially non-blocking and the space stage is relatively smaller. It is, therefore, most cost-effective for networks handling high traffic, However, for still higher traffic handling capacity networks, e.g., tandom exchanges, it may be desirable to use TSST or TSSST architecture.
The choice of a particular architecture is dependent on other factors also, viz., implementation complexity, modularity, testability, expandability, etc. As a large number of factors favor the TST structure, it is most widely used.
4.7 TST Network
As the name suggests, in a TST network, there are two-time stages separated by a space stage. The former carries out the function of time-slot changing, whereas the latter performs highway jumping. Let us consider a network having n input and n output PCM highways. Each of the input and output time stages will have n time switches and the space stage will consist of an n x n cross point matrix. The speech memory, as well as the control memory of each time switch and each column of a control memory of the space switch, will have m locations, corresponding to m time-slots in each PCM. Thus, it is possible to connect any TS in I/C PCM to any TS in O/G PCM.
In the case of local exchange, the network will be of the folded type, i.e., the O/G PCM highways, via a suitable hybrid. Whereas, for a transit exchange, the network will be non-folded, having complete isolation of I/C and O/G PCM highways. However, a practical local exchange will have a combination of both types of networks.
For the sake of explanation, let us assume that there are only four I/C and O/G PCM highways in the network. Hence, there will be only four-time switches in each of the T-stages and the space switch will consist of a 4×4 matrix. let us consider an objective of connecting two subscribers through this switching network of local exchange, assuming that the CC assigns TS4 on HWY0 to the calling party and TS6 on HWY3 to the called party
The speech samples of the calling party have to be carried from TS4 of I/C HWY 0 and to TS6 of O/G HWY3 and those of the called party from TS6 of I/C HWY 3 to TS4 of O/G HWY 0, with the help of the network. The CC establishes the path, through the network in three steps. To introduce greater flexibility, it uses an intermediate time-slot, TSx, which is also known as internal time-slot. The three switching steps for transfer of speech sample of the calling party to the called party are as under:
Step 1 Input Time Stage (IT) TS4 HWY0 to TSx HWY0
Step 2 Space stage (S)Tsx HWY0 to Tsx HWY3
Step 3 Output Time Stage (OT)Tsx HWY3 to TS6 HWY3
As the message can be conveyed only in one direction through this path, another independent path, to carry the message in the other direction is also established by the CC, to complete the connection. Assuming the internal time-slots to be TS10 and TS11, the connection may be established as shown in fig 6.
Let us now consider the detailed switching procedure making some more assumptions for the sake of simplicity. Though practical time switches can handle 256 time-slots in parallel mode, let us assume serial working and that there are only 32 time-slots in each PCM. Accordingly, the speech and control memories in time switches and control memory columns in the space switch will contain 32 locations each.
To establish the connection, the CC searches for free internal time-slots. Let us assume that the first available time-slots are TS10 and TS11, as before. To reduce the complexity of control, the first time stage is designed as an output-controlled switch, whereas the second time stage is input-controlled.
For transfer of speech samples from the calling party to the called party of the previous example, CC orders writing of various addresses in location 10 of control memories of IT-10, OT-3 and column 3 of CM-S of corresponding to O/G highway, HWY3. Thus, 4 correspondings to I/C TS4 is written in CM-IT-0, 6 correspondings to O/G TS6 is written in CM-OT-3 and 0 correspondings to I/C HWY 0 is written in column 3 of CM-S, as shown in fig. 7.
As the first time switch is output-controlled, the writing is done sequentially. Hence, a sample, arriving in TS4 of I/C HWY 0, is stored in location 4 of SM-IT-0. It is a readout on internal HWY 0 during TS10 as per the control address sent by CM-IT-0. In the space switch, during this internal TS10, the cross point 0 in column 3 is enabled, as per the control address sent by column 3 of CM-S, thus, transferring the sample to HWY3. The second time stage is input controlled and hence, the sample, arriving in TS10, is stored in location 6 of SM-OT-3, as per the address sent by the CM-OT-3. This sample is finally, readout during TS6 of the next frame, thus, achieving the connection objective.
Similarly, the speech samples in the other direction, i.e., from the called party to the calling party, are transferred using internal TS11. As soon as the call is over, the CC erases the contents in memory locations 10 and 11 of all the concerned switches, to stop the further transfer of the message. These locations and time-slots are, then, avialable to handle the next call.
4.8 Switching Network Configuration of some Modern Switches
- E10B – T-S-T
- EWSD – T-S-S-S-T
- AXE10 – T-S-T
- CDOT(MBM) – T-S-T
- 5ESS – T-S-T
- OCB 283 – T