Digital Multiplexing Concepts, Signal Justification & Control and Jitter
The functions of digital multiplex equipment are to combine a defined integral number of digital input signals (called tributaries) at a defined digit rate by time division multiplexing and also to carry out the reverse process (demultiplexing).
In analogue system, multiplex equipment uses F.D.M. to assemble individual channels into groups, super group etc. Similarly, in digital systems, hierarchical levels have been defined using T.D.M. and are identified by their digit rate measured in bit/sec.
|Bit rate Mbit/sec.||No. of channels|
The digital signals which are to be multiplexed may be synchronous to one clock (called master clock) or they may not be synchronous (called asynchronous signals).
3.0 MULTIPLEXING OF SYNCHRONOUS DIGITAL SIGNALS
The various tributary bit streams are synchronous and operate at the same rate defined as T bit/sec. To multiplex ‘n’ such tributaries the rate of multiplex output should be nT bit/s. The method adopted for multiplexing such n signals into one stream may be as follows :
- Block interleaving :
Bunch of information taken at a time from each tributary and fed to main multiplex output stream. The memory required will be very large.
- Bit interleaving :
A bit of information taken at time from each tributary and fed to main multiplex output stream in cyclic order, a very small memory is required.
At the demultiplex end, it is necessary to recognise which bit of information belongs to which tributary. This could be achieved by transmitting a fixed code after a fixed number of information bits called “frame”. The fixed code is called frame alignment signal. It is recognised first and received frame of information is aligned to this fixed code.
This method of multiplexing is easy but not reliable. If any deviation in nominal bit rate of a tributary occurs, it will cause loss of time slot and hence loss of information.
Here, various tributaries operate at different bit rates.
Two signals are asynchronous at their corresponding significant instant occur at nominally the same rate, any variation in rate being constrained within specified limits.
When nominal bit rate of tributaries are within specified limit. It is necessary to synchronize the tributary signal with a common nominal bit rate of multiplexer derived from timing generator of multiplexer. The synchronization is done in such a way that there is no loss of information. The process adopted for such synchronization is called “Pulse stuffing” or justification. Justification is a process of changing the rate of digital signals in a controlled manner. There are three types of justification processes :
- Positive justification : Common synchronization bit rate offered at each tributary is higher than the bit rate of individual tributary.
- Positive-negative justification : Common synchronization bit rate offers is equal to the nominal value.
- Negative justification : Common synchronization bit rate offered is less than the nominal value.
Fig. 1(a) shows a configuration where the outputs of two PCM transmitters A&B are to be multiplexed in the combiner. If A and B are synchronous, they can be easily multiplexed by the combiner as shown in Fig. 1(b). Generally, however, A&B are clocked by separate clock sources of asynchronous. In this case multiplexing is not successively accomplished simply by the use of combiner owing to the occurrence of pulse phase fluctuations and/or pulse amplitude superposition as can be seen in Fig.1(c).
- RETIMING ASYNCHRONOUS SIGNALS BY JUSTIFICATION
Figure 2 shows a system for explaining the principle of the multiplexer for successfully multiplexing plural asynchronous signals. The waveforms appearing at various points in Fig.2 are shown in Fig.3. An asynch. input pulse train A is written into MEM I comprising several elements. The writing pulse train C whose bit rate is f is extracted from A at a clock extraction (CLK EXT I). On the other hand, the written information is read out of MEM I with a sufficient phase lag with respect to time of writing in. Through an inhibit gate (INH GATE I), the reading pulse train D is obtained by dividing the output bit rate nf (1+ Δ) of a common clock generator (CLK GEN) at a bit rate divider (DIV 1).
n – no. of asynch. signals to be multiplexed.
Δ – clock increase rate.
As the bit rate of the reading pulse train D is set at (f+ Δ f) which is higher than any value of f, the time of read out (D) gradually approaches that of write in ©. The phase difference between C&D is monitored by a phase comparator of COMP I and just before the difference reaches zero, a pulse is applied to the inhibit input of INH GATE I from a control circuit (CONT I) to inhibit the gate. At this moment, with one bit of the reading pulse train D being removed, the reading operation pauses and an information less pulse (or justification pulse) is inserted into the read out pulse train E. the time of read out (D) at the same time is again set to a sufficient lag with respect to time write in (G). As all the signals read out of the respective memories are now retimed by timing pulses derived from the common CLK GEN, they are now easily multiplexed as F in Fig.3 at the combiner (COMB).
The information pulses inserted into E (those hatched in Fig. 3) and this sort of retiming method are respectively called “justification pulses” and “justification”. The information whether or not justification has been performed, is inserted into F and COMB and transmitted to the receiving side.
6.0 RECOVERING ORIGINAL SIGNALS BY DEJUSTIFICATION
The justification pulses have to be removed at the receiving side to perfectly recover the original signals. This operation is called “dejustification”.
The transmitted pulse train F from the line is received and demultiplexed at distributor (DIST). One of the demultiplexed signal E that corresponds to A, is written into memory MEM 2. The writing pulse train G whose bit rate is Δis obtained through an ingibit grate (INH GATE 2) by dividing the output bit rate nf(1+ Δ f) of clock extractor (CLK EXT2). On the other hand, the written information is read out of MEM 2 with a slight phase lag with respect to the time of write in. The reading pulse train H, whose bit rate is f, is applied from voltage controlled oscillator (VCO). As the bit rate of the reading pulse train H is lower than that of the writing pulse train G, the time of read out (H) gradually drifts away from that of write in (G). Just before a justification pulse in E (ONE of these hatched in Fig.3) is written into MEM 2, the information, telling that the justification has been performed is applied from DIST to a control circuit (CONT 2). Then a pulse is applied to the inhibiting input of INH GATE 2 from CONT 2 to inhibit the gate.
At this moment, with one bit of the writing pulse train G being removed, the writing operation pauses and the justification pulse is removed or dejustified. At the same time, the time of read out (H) again set to be very close to the time of write in (G). As the reading operation does not pause, the original signal is recovered as ‘A’. The phase difference between G and H is monitored by a phase comparator (COMP 2), and the low frequency components of the output voltage of COMP 2 are applied to VCO through a low pass filter (LPF). Thus, the jitter introduced due to dejustification into the read out pulse train ‘A’ is sufficiently suppressed. The loop formed by VCO, COMP and LPF is called a “Phase controlled loop”.
Figure 4 gives the frame structure for 34 Mbits/sec system.
7.0 JUSTIFICATION CONTROL SIGNAL
Justification control signal indicates at demultiplexer the presence of justifiable bit in the frame. To avoid errors present in the justification control bit, more than one bit is transmitted as control bit and majority decision is taken at demultiplexer.
Normally 3 or 5 bits (3 bits in case of 8 and 34 Mbits systems and 5 bits in 140M bits system) are transmitted per tributary per frame as justification control bits and 2 or 3 bits present at demultiplexer out of 3 or 5 bits transmitted are taken as majority decision and it is assumed that justifiable bit is present in the frame. These 3 or 5 bits of justification control bits per tributary per frame are distributed in the frame. Two or three digital errors are required to cause false information of justification (loss of one digit or addition of one digit) which results in a loss of frame alignment in lower hierarchical levels.
HARDWARE REALIZATION OF DIGITAL MULTIPLEX SYSTEM
System are realized by digital circuits using TTL and ECL ICs. The typical gate delays and toggling speeds of the different series of ICs are given below :
|Propagation delays (typical)||Toggling speed (typical)|
|LS series TTL||15 ns||25 MHz|
|S series TTL||5 ns||75 MHz|
|10,000 series ECL||3 ns||200 MHz|
As is is evident from the above rates that LS series is suitable only till 8 MHz system, where as S series is suitable for 34 MHz system and 10,000 series is being used for 140 MHz system.
9.0 TRANSMIT TRIBUTARY
The information from tributary is written in an elastic memory with tributary clock derived from incoming signal. Elastic memory is read out by a clock which is faster than the clock of its own. Reading clock is derived from common transmit clock (Common synchronization clock). The reading clock is of rate F2/n (where n is the no. of tributaries and F2 is output frequency of multiplexer for ex. 34,368/4 for 34M bit system) with gaps where non information bit occurs in the frame structure (i.e., for frame alignment signal and justification control bit, service digits). Since read clock always operates faster than write clock, it is required to stop read clock for a bit and insert non-information bit-justification bit. The information which read out from memory contains information bit, justification control bit and justifiable bit. The decision when to insert the justifiable bit is taken when linearly increasing phase difference crosses a threshold level. The threshold value is selected in such a way that average rate of read clock is equal to the write clock rate.
In the demultiplexer, the clock timing of the input multiplex signal enables a control on the timing of operations. The detection of frame alignment signals enables the receive frame to be aligned with the transmit frame which enables the receiver to demultiplex the tributary information. This tributary information is written in elastic memory as in transmit tributary by the clock derived from receive clock. A phase locked oscillator is used to read the elastic memory with a timing rate equal to the average write clock and, therefore, equal to that of the corresponding tributary signal at the input of the multiplexer.
10.0 JITTER ASPECT OF MULTIPLEX EQUIPMENT
While considering the jitter aspect of the multiplex system, different types of jitter introduced in the systems are taken into account such as :
- Jitter introduced due to the routine insertion of the frame alignment words and of the service digits and justification instructions.
- Justification jitter.
- Waiting time jitter.
The first two jitter components are at high frequencies in relation to the pass band of the P.L.L. and hence filtered out, whereas waiting time jitter which is due to phase difference between write and read clock and varies from frame to frame, has a low frequency component and cannot be jittered out by P.L.L. at the demultiplexer output.
- LINE INTERFACE
The output of multiplexer is purely a unipolar digital signal having D.C. voltage. Normally cable are balanced, having no DC component, or minimum DC to avoid cross talk. Any code such as AMI, HDB3, CMI can be chosen, which are bipolar in nature. These line codes are selected in such a way that :
- Timing signal at the receiver could be extracted easily, hence it should contain enough timing information. Timing signal extraction circuit has limitations because of the “Q factor” of the coil used in the circuit. Higher the Q of coil, the costlier it is.
- The bandwidth of the signal is kept small. The energy in the upper part of the frequency spectrum should be small in order to avoid attenuation distortion caused by high transmission loss at higher frequency.
- The energy in the lower part of the frequency spectrum should also be kept small in order to reduce the interference from voice frequency circuit in the same cable and vice-versa.
- It should have no DC component which could be obtained by selecting a code having minimum digital sum variation.
The output of 2, 8 and 34 MBit systems is in HDB3 code. Rules followed for HDB3 line code are as follows :
- Every sequence of four consecutive zeros is replaced by either 000V or B00V, where B is a normal bipolar mark and V is a mark violating the AMI sequence.
- Sequence 000V or B00V is used such that the number of bipolar pulses between successive violation pulse is odd. This ensures that violation pulses, form their own bipolar sequence.
The output of 140 MBit system is in CMI code, where the coding rule is as follows :
|Binary element||CMI code|
|1||00 } transmitted
11 } alternately