Hardware Architecture AN-RAX


Hardware Architecture AN-RAX

  • OVERVIEW
    The integrated circuits used in the C-DOT 256P AN-RAX hardware have low power dissipation and high operational reliability. The components used are based on Metal-Oxide Semiconductor (MOS), Complementary MOS (CMOS), Low-Power Schottky Transistor-Transistor Logic (LSTTL), and bipolar technologies. All the system circuitry has been packaged into seven card types. On the broad level these could be divided into following categories:
  • Terminal Interfaces

Subscriber Line Card (LCC/CCM)

  • Controller Cards

AN-RAX Controller Card (ARC)

AN-RAX Interface Card (ARI)

Signalling Processor Card (SPC) or Integrated Signalling Processor Card(ISP)

  • Service Cards

RAX Terminal Tester Card (RTC)

  • Power Supply Unit (PSU-I)

 

  • TERMINAL INTERFACES
    C-DOT 256P AN-RAX uses Subscriber Line Card (LCC/CCM) to provide Analog Terminal Interface. Each terminal interface card caters to 8 terminations. Four cards make a Terminal Group (TG) which is associated with PCM 32 channel link towards the ARC card. Signalling information are multiplexed and placed on 4 wire ABCD signalling bus toward SPC/ISP card.Subscriber Line Card (LCC/CCM) (Ref. Fig. 4.1)
    Line Circuit Card (LCC) is used to interface ordinary subscriber lines. Fig. 4.1 gives the detailed block diagram of this card.
    The Line Circuit Card performs a set of functions collectively termed as BORSCHT, signifying:

B – Battery Feed

O – Overvoltage Protection

R – Ringing

S – Supervision

C – Coding

H – Hybrid Conversion

T – Testing

  • Battery Feed
    A -48V_+ 4V battery with current limiting facility is provided on each line for signalling purposes and for energising the microphone.
  • Overvoltage Protection
    A hybrid transformer and surge arresters across Tip and Ring provide protection against over voltages.
  • Ringing
    Ringing is extended to subscribers under the control of Signalling Processor (SPC/ISP card), through the contacts of an energized relay. The Ring is tripped when off-hook condition is detected.
  • Supervision
    On/Off-hook detection and dialling make/break are encoded and passed on to SPC/ISP card as the scan information from the subscriber lines.
  • Coding
    Coding refers to encoding of analog voice to digital form (8 bit, A-law PCM) through a coder/decoder (codec). Codec outputs of 32 codecs of each Terminal Group are time division multiplexed to form a PCM 32 channel at 2.048 Mbps.
  • Hybrid Conversion
    2-wire to 4-wire conversion is done before coding for full duplex (voice) operation.
  • Testing
    Metallic access is provided on subscriber lines for routine test. (Tests Access Relays)
  • Coin Collection Box (CCB) interface card is an ordinary LCC card with an additional reversal relay per subscriber to extend reversal on called party answer. This card is basically used to cater to special requirements of PCOs and PABXs. However, this card can also be used as line circuit card (LCC).
    Coin Collection Box with Metering (CCM) card is also same as LCC/CCB card except that it has got extra hardware to generate and feed 16 KHz pulses towards subscriber premise. This card is basically used to interface STD PCOs or special subscribers having home metering requirements. However, in CCM card out of eight ports only last two i.e., Port no. 7 and 8 are equipped with 16 KHz pulse generator. Therefore, only two subscribers per CCM card may have this provision. Rest of the ports are used for ordinary subscribers or coin collection box type. This card as a whole can be used as LCC.
  • CONTROLLER CARDS
    The ARC card functions as the main controller of the AN-RAX. It performs time switching of voice/data slots between line cards. Towards the line cards it gives the card select, subscriber select, clock and sync signals. It has an interface towards the SPC/ISP card for providing signalling interface to the line cards. It has an interface towards the ARI (AN-RAX Interface) card used in slave frame to support voice and signaling interface for the line cards in the slave frame. The card exists in copy duplication and occupies slots 12 and 15 of the master frame in 256P AN-RAX. It interfaces with RTC (RAX Terminal Tester) card for supporting terminal testing in AN-RAX.

Line Circuit card

  • FUNCTIONAL DESCRIPTION

The Functional Blocks of ARC are :

Processor and memory block

Time switch and service circuits block

SPC/ISP interface block

Digital trunk interface block

DT clock extraction and generation block

ARI interface block

PSU interface block

ARC Card Diagram

Processor Block & Memory Mapped Device

  • Processor and Memory Block
    This card is designed using Morotola’s 68392 processor in MASTER-SLAVE configuration as shown in the Fig. 4.3. The processor is clocked at 16.384 MHz. The processor clock is generated using a crystal oscillator. The reset circuitry uses a micro monitor chip, which asserts reset when VCC is out of range or when manual reset switch is activated or when strobe is missing. The 16.38 MHz processor input clock is divided by two and given as strobe to the micro monitor chip.
    Communication Block
    The master IMP’s SCC1 is used as HDLC link towards RTC card or ETT card. SCC will operate in NMSI mode at 64 Kbps for RTC card and in PCM mode at 2 Mbps for ETT card.
    Master IMP’s SCC2 is used as HDLC link towards duplicate ARC card. Speed of this link is 64Kbps.
    Master IMP’s SCC3 is used as debugging ACIA link. Speed of this link is software programmable and normally is 9600 baud.
    SCP of Master IMP is used to communicate with tester card in ARC card tester. Slave IMP’s SCC1 & SCC2 are used in PCM mode.
    SCC1 is used to handle HDLC messages (V5.2) on DT0 link. SCC2 is used to handle HDLC messages (V5.2) on DT1 link.
    Slave IMP’s SCC3 is used as an ACIA link for providing MMI through a dumb terminal. Speed of this link is S/W programmable and normally is 9600 baud.
    Slave IMP’s SCP is used to access DT ASIC (CPRAC) registers in order to control and monitor the DT links. In this communication, processor is always the master.
    Timers Block
    Master IMP’s Watchdog timer is used as software watchdog. The timer reference register is initialised with the time-out value. Software periodically resets the counter so that the timer count register never reaches the time-out count. If software fails to reset the timer count register within the stipulated time, timer count reaches the reference count and a level 7 interrupt is raised to IMP and also to mate ARC card.
    Timer 1 of master IMP is used as RTC (Real Time Clock). This timer can be programmed to periodically interrupt the processor at regular intervals.
    Timer 2 of master IMP is used as counter or timer in ARC card tester.
    Timer 1 of slave IMP is used as DT0 slip detector/counter. The counter can be programmed to count the number of slip’s occurring in DT link for statistical health monitoring of the DT link
    Timer 2 of slave IMP is used as DT1 slip detector/counter.
    Real Time Calendar
    The ARC card has been provided with one Real Time Clanedar chip, which can count the time, date, day of the week & Year. At present, this is not used.
    Control and Status Registers Block
    The Port A and Port B registers of master and slave processors are used as control and status registers. Some of the control and status registers are implemented externally using programmable devices. They are used to latch the status of all interrupts and to clear the latched status, program loop back bits and to latch ID bits from the back plane.
    Interrupt Logic Block
    This block receives all error interrupts and peripheral interrupts, prioritizes them and inputs to master IMP. Some interrupts are given directly to the Port B interrupt pins of master and slave at level 4. All the events are latched and the status is provided to the processor through status registers. The processor can clear the latched events by appropriately setting the corresponding bits in the control registers. Interrupt from SPC/ISP card master frame and slave frame are combined and presented at level 5. Error signals from Master and slave PSU cards are combined to generate a level 1 interrupt to the processor.
    Memory Block
    This card supports onboard memory of 1MB FLASH or 2MB EPROM, 1MB RAM and 64 KB/1MB NVRAM. Chip selects are generated using master and slave IMP’s chip select registers and glue logic. One jumper is provided to select either FLASH or EPROM and one more jumper is provided to select NVRAM capacity.
  • Time Switch and Service Circuits Block This card has a 2K by 2K time switch, implemented in FPGA. The time switch is operated at 8MHz speed and is used in 16 bit processor mode. One input link is programmed as conference link. Speed of the conference link is 8Mbps and it supports 32 Four party conferencing. 12 out of 16 possible I/O links are used as shown below.

    The input links of the time switch are :

  1. One conference link (8Mbps) for 32 four party conferencing
  2. One 8Mbps link from Tone, Announcement, MF and DTMF generation circuit.
  3. Eight 2Mbps links (TG (0)_IN to TG (7)_IN) from TGs.
  4. One 2Mbps link for DT and ETT messages
  5. Two 2Mbps links from DTs

The output links of the time switch are :

  1. One link for conferencing (8Mbps)
  2. Eight 2 Mbps links (TG (0)_OUT to TG (7)_OUT) towards TGs.
  3. One 2 Mbps link for DT and ETT messages
  4. Two 2 Mbps links towards DTs.

Time Switch input/Output Link UsageTone, Announcement, MF-DTMF Generation
The MF, DTMF, tone and announcement samples are stored in EPROMs. The EPROMs are addressed by free running counter chains, which are implemented in FPGAs. Bank control EPROMs are used to address different pages of the stored data. Parallel output of EPROMs are converted to serial link at 8 Mbps and connected to time switch as shown in Fig. 4.6.

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