Due to the reduced bit rate in parallel mode, the cross point is required to be operated only for 1/8th of the time required for serial working. It can, thus, be shared by eight times more channels, i.e., 32 x 8 = 256 channels, in the same frame.
However, since the eight bits of one TS are carried on eight wires, each
cross point has eight switches to interconnect eight input wires to eight output wires. Each cross point (all the eight switches) will remain operated now for the duration of one bit only, i.e., only for 488 ns (1/8th of the TS period of 3.9 µs).
For example, to connect 40 PCM I/C highways, a matrix of 40x 40 = 1600
cross points each having a single switch is required in serial mode working. Whereas in parallel mode working, a matrix of (40/8 x 40/8) = 25 cross point is sufficient. As eight switches are required at each cross point 25 x 8 = 200 switches only are required. Thus, there is a reduction of the matrix by 1/8th in parallel mode working, hence a reduction in size and cost of the switching matrix.
4.3 Digital Time Switch
A Digital Time Switch consists of two memories, viz., a speech or buffer memory to store the samples till destination time-slots arrive, and control or connection or address memory to control the writing and reading of the samples in the buffer memory and directing them on to the appropriate time-slots.
Speech memory has as many storage locations as the number of time-slots in input PCM, e.g., 32 locations for 32 channel PCM system.
The writing/reading operations in the speech memory are controlled by the Control Memory. It has the same number of memory locations as for speech memory, i.e., 32 locations for 32 channel PCM system. Each location contains the address of one of the speech memory locations where the channel sample is either written or read during a time-slot. These addresses are written in the control memory of the CC of the exchange, depending upon the connection objective.
A Time-Slot Counter which usually is asynchronous binary counter is used to count the time-slots from 0 to 31, as they occur. At the end of each frame, It gets reset and the counting starts again. It is used to control the timing for writing/reading of the samples in the speech memory.
Consider the objective that TS4 of incoming PCM is to be connected to TS6 of outgoing PCM. In other words, the sample arriving in TS4 on the I/C PCM has to be delayed by 6 – 4 = 2 time-slots, till the destination time-slot, viz., TS6 appears in the O/G PCM. The required delay is given to the samples by storing it in the speech memory. The I/C PCM samples are written cyclically i.e. sequentially time-slot wise, in the speech memory locations. Thus, the sample in TS4 will be written in location 4, as shown in fig.4.
The reading of the sample is controlled by the Control Memory. The Control Memory location corresponding to output time-slot TS6 is 6. In this location, the CC writes the input time-slot number, viz.,4, in binary. These contents give the read address for the speech memory, i.e., it indicates the speech memory locations from which the sample is to be read out, during the reading cycle.
When the time-slot TS6 arrives, the control memory location 6 is read. Its content addresses location 4 of the speech memory in the read mode and the sample is read on to the O/G PCM.
In every frame, whenever time-slot 4 comes a new sample will be written in location 4. This will be read when TS6 occurs. This process is repeated until the call lasts.
For the disconnection of the call, the CC erases the contents of the control memory location to halt the further transfer of samples.
Time switch can operate in two modes, viz.,
- Output associated control
- Input associated control
4.3.1 Output associated control
In this mode of working, 2 samples of I/C PCM are written cyclically in the speech memory locations in the order of time-slots of I/C PCM, i.e., TS1 is written in location 1, TS2 is written in location 2, and so on, as discussed in the example of Sec.4.2.
The contents of speech memory are read on output PCM in the order specified by control memory. Each location of control memory is rigidly associated with the corresponding time-slot of the O/G PCM and contains the address of the TS of incoming PCM to be connected to. The control memory is always read cyclically, in synchronism with the occurrence of the time-slot. The entire process of writing and reading is repeated in every frame until the call is disconnected.
It may be noticed that the writing in the speech memory is sequential and independent of the control memory, while reading is controlled by the control memory, i.e., there is a sequential writing but controlled reading.
4.3.2 Input associated control
Here, the samples of I/C PCM are written in a controlled way, i.e., in the order specified by control memory, and read sequentially.
Each location of control memory is rigidly associated with the corresponding TS of I/C PCM and contains the address of TS of O/G PCM to be connected to.
The previous example with the same connection objective of connecting TS4 of I/C PCM to TS6 of O/G PCM may be considered for its restoration. Location 4 of the control memory is associated with incoming PCM TS4. Hence, it should contain the address of the location where the contents of TS4 of I/C PCM are to be written in speech memory. A CC writes the number of the destination TS, viz., 6 in this case, in location 4 of the control memory. The contents of TS4 are, therefore, written in the location of speech memory, as shown in fig5.
The contents of speech memory are read in the O/G PCM in a sequential way, i.e., location 1 is read during TS1, location 2 is read during TS2, and so on. In this case, the contents of location 6 will appear in the output PCM at TS6. Thus the input PCM TS4 is switched to output PCM TS6. In this switch, there is sequential reading but controlled writing.