Digital Multiplexing Concepts, Signal Justification & Control and Jitter
The functions of digital multiplex equipment are to combine a defined integral number of digital input signals (called tributaries) at a defined digit rate by time division multiplexing and also to carry out the reverse process (demultiplexing).
In analogue system, multiplex equipment uses F.D.M. to assemble individual channels into groups, super group etc. Similarly, in digital systems, hierarchical levels have been defined using T.D.M. and are identified by their digit rate measured in bit/sec.
|Bit rate Mbit/sec.||No. of channels|
The digital signals which are to be multiplexed may be synchronous to one clock (called master clock) or they may not be synchronous (called asynchronous signals).
3.0 MULTIPLEXING OF SYNCHRONOUS DIGITAL SIGNALS
The various tributary bit streams are synchronous and operate at the same rate defined as T bit/sec. To multiplex ‘n’ such tributaries the rate of multiplex output should be nT bit/s. The method adopted for multiplexing such n signals into one stream may be as follows :
- Block interleaving :
Bunch of information taken at a time from each tributary and fed to main multiplex output stream. The memory required will be very large.
- Bit interleaving :
A bit of information taken at time from each tributary and fed to main multiplex output stream in cyclic order, a very small memory is required.
At the demultiplex end, it is necessary to recognise which bit of information belongs to which tributary. This could be achieved by transmitting a fixed code after a fixed number of information bits called “frame”. The fixed code is called frame alignment signal. It is recognised first and received frame of information is aligned to this fixed code.
This method of multiplexing is easy but not reliable. If any deviation in nominal bit rate of a tributary occurs, it will cause loss of time slot and hence loss of information.
Here, various tributaries operate at different bit rates.
Two signals are asynchronous at their corresponding significant instant occur at nominally the same rate, any variation in rate being constrained within specified limits.
When nominal bit rate of tributaries are within specified limit. It is necessary to synchronize the tributary signal with a common nominal bit rate of multiplexer derived from timing generator of multiplexer. The synchronization is done in such a way that there is no loss of information. The process adopted for such synchronization is called “Pulse stuffing” or justification. Justification is a process of changing the rate of digital signals in a controlled manner. There are three types of justification processes :
- Positive justification : Common synchronization bit rate offered at each tributary is higher than the bit rate of individual tributary.
- Positive-negative justification : Common synchronization bit rate offers is equal to the nominal value.
- Negative justification : Common synchronization bit rate offered is less than the nominal value.
Fig. 1(a) shows a configuration where the outputs of two PCM transmitters A&B are to be multiplexed in the combiner. If A and B are synchronous, they can be easily multiplexed by the combiner as shown in Fig. 1(b). Generally, however, A&B are clocked by separate clock sources of asynchronous. In this case multiplexing is not successively accomplished simply by the use of combiner owing to the occurrence of pulse phase fluctuations and/or pulse amplitude superposition as can be seen in Fig.1(c).
- RETIMING ASYNCHRONOUS SIGNALS BY JUSTIFICATION
Figure 2 shows a system for explaining the principle of the multiplexer for successfully multiplexing plural asynchronous signals. The waveforms appearing at various points in Fig.2 are shown in Fig.3. An asynch. input pulse train A is written into MEM I comprising several elements. The writing pulse train C whose bit rate is f is extracted from A at a clock extraction (CLK EXT I). On the other hand, the written information is read out of MEM I with a sufficient phase lag with respect to time of writing in. Through an inhibit gate (INH GATE I), the reading pulse train D is obtained by dividing the output bit rate nf (1+ Δ) of a common clock generator (CLK GEN) at a bit rate divider (DIV 1).
n – no. of asynch. signals to be multiplexed.
Δ – clock increase rate.
As the bit rate of the reading pulse train D is set at (f+ Δ f) which is higher than any value of f, the time of read out (D) gradually approaches that of write in ©. The phase difference between C&D is monitored by a phase comparator of COMP I and just before the difference reaches zero, a pulse is applied to the inhibit input of INH GATE I from a control circuit (CONT I) to inhibit the gate. At this moment, with one bit of the reading pulse train D being removed, the reading operation pauses and an information less pulse (or justification pulse) is inserted into the read out pulse train E. the time of read out (D) at the same time is again set to a sufficient lag with respect to time write in (G). As all the signals read out of the respective memories are now retimed by timing pulses derived from the common CLK GEN, they are now easily multiplexed as F in Fig.3 at the combiner (COMB).
The information pulses inserted into E (those hatched in Fig. 3) and this sort of retiming method are respectively called “justification pulses” and “justification”. The information whether or not justification has been performed, is inserted into F and COMB and transmitted to the receiving side.
6.0 RECOVERING ORIGINAL SIGNALS BY DEJUSTIFICATION
The justification pulses have to be removed at the receiving side to perfectly recover the original signals. This operation is called “dejustification”.
The transmitted pulse train F from the line is received and demultiplexed at distributor (DIST). One of the demultiplexed signal E that corresponds to A, is written into memory MEM 2. The writing pulse train G whose bit rate is Δis obtained through an ingibit grate (INH GATE 2) by dividing the output bit rate nf(1+ Δ f) of clock extractor (CLK EXT2). On the other hand, the written information is read out of MEM 2 with a slight phase lag with respect to the time of write in. The reading pulse train H, whose bit rate is f, is applied from voltage controlled oscillator (VCO). As the bit rate of the reading pulse train H is lower than that of the writing pulse train G, the time of read out (H) gradually drifts away from that of write in (G). Just before a justification pulse in E (ONE of these hatched in Fig.3) is written into MEM 2, the information, telling that the justification has been performed is applied from DIST to a control circuit (CONT 2). Then a pulse is applied to the inhibiting input of INH GATE 2 from CONT 2 to inhibit the gate.